View 74F399PC_1107148.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

74F398 * 74F399 Quad 2-Port Register
April 1988 Revised October 2000
74F398 * 74F399 Quad 2-Port Register
General Description
The 74F398 and 74F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flops on the rising edge of the clock. The 74F399 is the 16-pin version of the 74F398, with only the Q outputs of the flip-flops available.
Features
s Select inputs from two data sources s Fully positive edge-triggered operation s Both true and complement outputs--74F398
Ordering Code:
Order Number 74F398SC 74F398PC 74F399SC 74F399SJ 74F399PC Package Number M20B N20A M16A M16D N16E Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagrams
74F398 74F399
(c) 2000 Fairchild Semiconductor Corporation
DS009533
www.fairchildsemi.com
74F398 * 74F399
Logic Symbols
74F398 74F398
74F399
74F399
IEEE/IEC
Unit Loading/Fan Out
U.L. Pin Names S CP I0a-I0d I1a-I1d Qa-Qd Qa-Qd Description HIGH/LOW Common Select Input Clock Pulse Input (Active Rising Edge) Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs Register Complementary Outputs (74F398) 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA
-1 mA/20 mA -1 mA/20 mA
www.fairchildsemi.com
2
74F398 * 74F399
Functional Description
The 74F398 and 74F399 are high-speed quad 2-port registers. They select four bits of data from either of two sources (Ports) under control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit D-type output register is fully edgetriggered. The Data inputs (I0x, I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. The 74F398 has both Q and Q outputs.
Function Table
Inputs S I I h h I0 I h X X I1 X X I h Q L H L H Outputs Q (Note 1) H L H L
H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial Note 1: 74F398 only
Logic Diagram
*F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.fairchildsemi.com
74F398 * 74F399
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min)--74F399 4000V twice the rated IOL(mA)
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCH ICCL ICCH ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current (74F398) Power Supply Current (74F398) Power Supply Current (74F399) Power Supply Current (74F399) -60 25 25 22 22 4.75 3.75 -0.6 -150 38 38 34 34 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A mA mA mA mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 0V VO = HIGH VO = LOW VO = HIGH VO = LOW
www.fairchildsemi.com
4
74F398 * 74F399
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL Input Clock Frequency Propagation Delay CP to Q or Q 100 3.0 (Note 4) 3.0 VCC = +5.0V CL = 50 pF Typ 140 5.7 6.8 7.5 9.0 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 100 3.0 3.0 8.5 ns 10.0 Max MHz Units
Note 4: 74F398 3.3 ns
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW In to CP Hold Time, HIGH or LOW In to CP Setup Time, HIGH or LOW S to CP (F398) Setup Time, HIGH or LOW S to CP (F399) Hold Time, HIGH or LOW S to CP CP Pulse Width HIGH or LOW 3.0 3.0 1.0 1.0 7.5 7.5 7.5 7.5 0 0 4.0 5.0 Max TA = 0C to +70C VCC = +5.0V Min 3.0 3.0 1.0 1.0 8.5 8.5 8.5 8.5 0 0 4.0 5.0 ns ns ns Max Units
5
www.fairchildsemi.com
74F398 * 74F399
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
www.fairchildsemi.com
6
74F398 * 74F399
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
7
www.fairchildsemi.com
74F398 * 74F399
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
www.fairchildsemi.com
8
74F398 * 74F399 Quad 2-Port Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
www.fairchildsemi.com

▲Up To Search▲

Price & Availability of 74F399PC

	To Download 74F399PC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .